Eliminating Nondeterminism to Enable Chip-Level Test of Globally-Asynchronous Locally-Synchronous SoC’s

Globally asynchronous locally synchronous (GALS) clocking applied to a system-on-a-chip (SoC) results in a design in which each core is a synchronous block (SB) of logic whose locally generated clock has an independent frequency and phase. Data is exchanged between cores using an asynchronous communication protocol. The nondeterministic synchronization strategies used by most GALS architectures makes chip-level silicon debug and functional test difficult and costly. Deterministic GALS methodologies make dataflow assumptions which are valid in a very limited set of applications. This paper describes a novel deterministic GALS methodology called “synchro-tokens”. Parameterized wrapper logic with enough flexibility to be useful for a wide range of systems is added to the asynchronous input signals of SBs. The wrapper ensures that each transition, although arriving at the wrapper at a nondeterministic time, is sensed by the SB during a deterministic cycle of the local clock while the system remains globally asynchronous. Synchro-tokens supports synchronous debug and test methodologies, including those based on 1149.1 and P1500, which rely on deterministic system behavior.